1. The salient feature of Pentium is
a) superscalar architecture
b) superpipelined architecture
c) superscalar and superpipelined architecture
d) none of the mentioned
2. The number of stages of the integer pipeline, U, of Pentium is
a) 2
b) 4
c) 3
d) 6
3. Which of the following is a cache of Pentium?
a) data cache
b) data cache and instruction cache
c) instruction cache
d) none of the mentioned
4. The speed of integer arithmetic of Pentium is increased to a large extent by
a) on-chip floating point unit
b) superscalar architecture
c) 4-stage pipelines
d) all of the mentioned
5. For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of
a) super pipelined technique
b) multiple instruction issue
c) super pipelined technique and multiple instruction issue
d) none of the mentioned
computer architects employ the technique of multiple instruction issue.
6. Which of the following is a class of architecture of MII (multiple instruction issue)?
a) super pipelined architecture
b) multiple instruction issue
c) very small instruction word architecture
d) super scalar architecture
7. The compiler reorders the sequential stream of code that is coming from memory into a fixed size instruction group in
a) super pipelined architecture
b) multiple instruction issue
c) very long instruction word architecture
d) super scalar architecture
8. The architecture in which the hardware decides which instructions are to be issued concurrently at run time is
a) super pipelined architecture
b) multiple instruction issue
c) very long instruction word architecture
d) super scalar architecture
9. The CPU has to wait till the execution stage to determine whether the condition is met in
a) unconditional branch
b) conditional branch
c) pipelined execution branch
d) none of the mentioned
10. The memory device that holds branch target addresses for previously executed branches is
a) tristate buffer
b) RAM
c) ROM
d) branch target buffer
11. The interrupt for which the processor has highest priority among all the external interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
12. The interrupt for which the processor has highest priority among all the internal interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
13. In case of string instructions, the NMI interrupt will be served only after
a) initialisation of string
b) execution of some part of the string
c) complete string is manipulated
d) the occurrence of the interrupt
14. The NMI pin should remain high for atleast
a) 4 clock cycles
b) 3 clock cycles
c) 1 clock cycle
d) 2 clock cycles
15. The INTR signal can be masked by resetting the
a) TRAP flag
b) INTERRUPT flag
c) MASK flag
d) DIRECTION flag
16. For the INTR signal, to be responded to in the next instruction cycle, it must go …….. in the last clock cycle of the current instruction
a) high
b) low
c) high or low
d) unchanged
17. The status of the pending interrupts is checked at
a) the end of main program
b) the end of all the interrupts executed
c) the beginning of every interrupt
d) the end of each instruction cycle
18. Once the processor responds to an INTR signal, the IF is automatically
a) set
b) reset
c) high
d) low
19. If the pin LOCK (active low based) is low at the trailing edge of the first ALE pulse, then till the start of the next machine cycle, the pin LOCK (active low) is
a) low
b) high
c) low or high
d) none of the mentioned
20. With the trailing edge of the LOCK (active low), the INTA (active low) goes low and remains in it for
a) 0 clock cycle
b) 1 clock cycle
c) 2 clock cycles
d) 3 clock cycles
21. The time taken by the ADC from the active edge of SOC(start of conversion) pulse till the active edge of EOC(end of conversion) signal is called
a) edge time
b) conversion time
c) conversion delay
d) time delay
22. The popular technique that is used in the integration of ADC chips is
a) successive approximation
b) dual slope integration
c) successive approximation and dual slope integration
d) none
23. The procedure of algorithm for interfacing ADC contain
a) ensuring stability of analog input
b) issuing start of conversion pulse to ADC
c) reading digital data output of ADC as equivalent digital output
d) all of the mentioned
24. Which is the ADC among the following?
a) AD 7523
b) 74373
c) 74245
d) ICL7109
25. The conversion delay in successive approximation of an ADC 0808/0809 is
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 milliseconds
26. The number of inputs that can be connected at a time to an ADC that is integrated with successive approximation is
a) 4
b) 2
c) 8
d) 16
27. ADC 7109 integrated by Dual slope integration technique is used for
a) low cost option
b) slow practical applications
c) low complexity
d) all of the mentioned
28. Which of the following is not one of the phase of total conversion cycle?
a) autozero phase
b) conversion phase
c) signal integrate phase
d) deintegrate phase
29. Which of the following phase contain feedback loop in it?
a) autozero phase
b) signal integrate phase
c) deintegrate phase
d) none
30. In the signal integrate phase, the differential input voltage between IN LO(input low) and IN HI(input high) pins is integrated by the internal integrator for a fixed period of
a) 256 clock cycles
b) 1024 clock cycles
c) 2048 clock cycles
d) 4096 clock cycles
Answers
| 1-c | 2-b | 3-b | 4-c | 5-b |
| 6-d | 7-c | 8-d | 9-d | 10-d |
| 11-c | 12-b | 13-c | 14-d | 15-b |
| 16-a | 17-d | 18-b | 19-a | 20-c |
| 21-c | 22-c | 23-b | 24- | 25-b |
| 26-c | 27-d | 28-b | 29-a | 30-c |