1. In which of these modes, the immediate operand is included in the instruction itself?
a) register operand mode
b) immediate operand mode
c) register and immediate operand mode
d) none of the mentioned
2. In register address mode, the operand is stored in
a) 8-bit general purpose register
b) 16-bit general purpose register
c) SI or DI
d) all of the mentioned
3. In which of the following addressing mode, the offset is obtained by adding displacement and contents of one of the base registers?
a) direct mode
b) register mode
c) based mode
d) indexed mode
4. In which of the following addressing mode, the offset is obtained by adding displacement, with the contents of SI?
a) direct mode
b) register mode
c) based mode
d) indexed mode
5. The address of location of operand is calculated by adding the contents of any of the baseregisters, with the contents of any of index registers in
a) based indexed mode with displacement
b) based indexed mode
c) based mode
d) indexed mode
6. Which of the following is not a data type of 80286?
a) Ordinal or unsigned
b) ASCII
c) Packed BCD
d) none of the mentioned
1. integer
2. Ordinal (unsigned)
3. pointer
4. string
5. ASCII
6. BCD
7. Packed BCD
7. The representation of 8-bit or 16-bit signed binary operands using 2′s complement is a data type of
a) Ordinal
b) ASCII
c) Packed BCD
d) integer
8. The instruction that pushes the general purpose registers, pointer and index registers on to the stack is
a) POPF
b) PUSH Imd
c) PUSH*A
d) PUSHF
9. While executing the PUSH*A instruction, the stack pointer is decremented by
a) 1 bit
b) 2 bits
c) 4 bits
d) 16 bits
10. The statement that is true for the instruction POP*A is
a) flags are uneffected
b) no operands are required
c) exceptions generated are same as that of PUSH*A
d) all of the mentioned
11. The mnemonic that is placed before the arithmetic operation is performed is
a) AAA
b) AAS
c) AAM
d) AAD
12. The Carry flag is undefined after performing the operation
a) AAA
b) ADC
c) AAM
d) AAD
13. The instruction that adjusts the RPL (Requested Privilege Level) of the selector, to the numeric maximum of current selector RPL value is
a) LAR
b) VERR
c) LSL
d) APRL
14. In the RCL instruction, the contents of the destination operand undergoes function as
a) carry flag is pushed into LSB & MSB is pushed into carry flag
b) carry flag is pushed into MSB & LSB is pushed into carry flag
c) auxiliary flag is pushed into LSB & MSB is pushed into carry flag
d) parity flag is pushed into MSB & LSB is pushed into carry flag
15. The instruction that is used as prefix to an instruction to execute it repeatedly until the CX register becomes zero is
a) SCAS
b) REP
c) CMPS
d) STOS
.
16. Match the following
a) MOvSB/SW 1) loads AL/AX register by content of a string
b) CMPS 2) moves a string of bytes stored in source to destination
c) SCAS 3) compares two strings of bytes or words whose length is stored in CX register
d) LODS 4) scans a string of bytes or words
a) a-3,b-4,c-2,d-1
b) a-2,b-1,c-4,d-3
c) a-2,b-3,c-1,d-4
d) a-2,b-3,c-4,d-1
17. The instructions that are used to call a subroutine from a main program and return to the main program after execution of called function are
a) CALL,JMP
b) JMP,IRET
c) CALL,RET
d) JMP,RET
18. The instruction that unconditionally transfers the control of execution to the specified address is
a) CALL
b) JMP
c) RET
d) IRET
19. Which instruction cannot force the 8086 processor out of ‘halt’ state?
a) Interrupt request
b) Reset
c) both interrupt request and reset
d) Hold
20. NOP instruction introduces
a) Address
b) Delay
c) Memory location
d) None
21. If the stack flag is set, and condition code bit C1=1, then the stack is
a) full
b) overflown
c) underflown
d) empty
22. If the stack flag is set, and condition code bit C1=0, then the stack is
a) full
b) overflown
c) underflown
d) empty
23. The bits that affect the result of arithmetic operations like ADD, SUB, MUL, DIV are
a) condition code bits
b) rounding control bits
c) masking bits
d) precision control bits
24. The precision is decided by the
a) opcode
b) extended precision format
c) opcode or extended precision format
d) none of the mentioned
25. If Numeric Processor Write (NPWR) active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
26. If Numeric Processor Read (NPRD) active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
27. Which of the input line(s) indicate that the CPU is performing an escape operation, and enables 80287 to execute the next instruction?
a) NPWR (active low) and NPRD (active low)
b) NPS1 and NPS2 (active low)
c) NPS1 (active low) and NPS2
d) CMD0 and CMD1
28. For which pin of 80286 is the active low pin, BUSY of 80287, connected?
a) ERROR (active low)
b) BUSY (active low)
c) HLDA
d) TEST (active low)
29. If Clock Mode (CM) input pin is held low, then the CLK input is divided by
a) 1
b) 2
c) 3
d) 4
30. Which of the following pin is not involved in the interface of 80287 with 80286?
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
Answers
| 1-b | 2-d | 3-c | 4-d | 5-b |
| 6-d | 7-d | 8-c | 9-b | 10-d |
| 11-d | 12-d | 13-a | 14-a | 15-b |
| 16-d | 17-c | 18-b | 19-d | 20-b |
| 21-b | 22-c | 23-d | 24-c | 25-c |
| 26-b | 27-c | 28-d | 29-b | 30-c |