1. If the most significant bit of relative address byte is 1, then the short jump instruction is
a) forward jump
b) back jump
c) either forward or back jump
d) none
2. The first byte of an absolute jump instruction consists of
a) 3 LSBs of opcode and 5 MSBs of 11-bit address
b) 5 MSBs of opcode and 3 LSBs of 11-bit address
c) 6 MSBs of opcode and 1 LSB of 11-bit address
d) 5 LSBs of opcode and 3 MSBs of 11-bit address
of 11-bit address. The next byte carries the least significant 8 bits of the 11-bit address.
3. The third byte of the long jump instruction is
a) opcode
b) 5 LSBs of opcode
c) higher byte of jump location or subroutine
d) lower byte of jump location or subroutine
4. The absolute jump instruction is intended mainly for a jump within a memory space of
a) 2 bytes
b) 2 Kbytes
c) 2 Mbytes
d) none
5. The LJMP instruction is very useful in programming in the external code memory space of
a) 32 MB
b) 64 MB
c) 32 KB
d) 64 KB
6. Which of the following is not an unconditional control transfer instruction?
a) JMP
b) RET
c) JNC
d) CALL
7. The conditional control transfer instructions use
a) status flags
b) bits of bit addressable RAM
c) SFRs termed bit
d) all of the mentioned
8. Which of the following is not a conditional control transfer instruction?
a) JC
b) JBC
c) JNC
d) NONE
9. The mnemonic used to perform a subtraction of source with an 8-bit data and jumps to specifiedrelative address if subtraction is non-zero is
a) DJNZ
b) CJNE
c) JZ
d) JNC
10. The mnemonic, JNB is used to jump to the specified relative address only if
a) specified bit=1
b) specified bit=0
c) specified bit is non-recursive
d) none
11. The files that reside in the current drive and directory of the hard disk is
a) OBJ files
b) EXE files
c) SRC files
d) DEST files
12. The master processor stores the result buffers on to the hard disk with the filename as
a) .EXE file
b) .OBJ file
c) .EXE file with extension .RES
d) .OBJ file with extension .RES
13. The 8288 bus controller chip derives the signals
a) ALE
b) DEN
c) DT/R(active low)
d) all of the mentioned
14. The EXE files should not exceed the size of
a) 30 KB
b) 50 KB
c) 60 KB
d) 40 KB
15. A part of memory that can be addressed by more than one processor for communication is known as
a) memory module
b) bus window
c) RAM
d) memory management unit
16. When a subprocessor wants to communicate with the bus window, it informs the main processor to
a) enable control buffer
b) storage buffer
c) disable tristate buffer
d) translation look aside buffer
17. When the subprocessor completes its execution, then the status on the status lines shows
a) hold status
b) halt status
c) high status
d) low status
18. For MEMR(active low) and MEMWR(active low) operations the mode of isolation buffer should respectively be in
a) receiver mode, receiver mode
b) transmit mode, receiver mode
c) receiver mode, transmit mode
d) transmit mode, transmit mode
19. If the DIR pin of the isolation chip is high, then it enters into
a) receiver mode
b) virtual access mode
c) transmit or receive mode
d) transmit mode
20. The complete software system is divided into
a) main program
b) Interrupt routine IRT2 for first subprocessing the unit
c) Interrupt routine IRT3 for first subprocessing the unit
d) all of the mentioned
21. The number of CPIs(Clock Per Instruction) for an instruction of RISC processors is
a) 0
b) 1
c) 2
d) 3
22. Which of the following is not true about RISC processors?
a) addressing modes are less
b) pipelining is key for high speed
c) microcoding is required
d) single machine cycle instructions
23. The RISC processors that support variable length instructions are from
a) Intel
b) Motorola
c) AMD
d) Intel and Motorola
24. Which of the following is true about register windowing?
a) chips expose 32 registers to programmer
b) puts demands on multiplexers
c) puts enormous demands on register ports
d) all of the mentioned
25. The disadvantage of register windowing is
a) high speed
b) puts demands on multiplexers/register ports
c) consumes less cycles
d) doesn’t handle overflow/underflow
26. The register window is used to point the number of physical registers is
a) infinite
b) that are currently used
c) finite
d) that are unused
b) fetch instructions from registers
c) write result into a register
d) access an operand in data memory
1. Fetch instructions from memory
2. Read registers and decode the instructions
3. Execute the instructions or calculate an address
4. Access an operand in data memory
5. Write result into a register
28. When an instruction depends on the results of the previous instructions then
a) error occurs
b) software fault occurs
c) data dependency occurs
d) hardware fault occurs
29. The instructions that instruct the processor to make a decision about the next instruction to be executed are
a) data dependency instructions
b) branch instructions
c) control transfer instructions
d) none
30. The reason for which the RISC processor goes to idle state(or stall) is
a) delay in reading information from memory
b) poor instruction set design
c) dependencies between instructions
d) all of the mentioned
Answers
| 1-b | 2-d | 3-c | 4-b | 5-d |
| 6-c | 7-d | 8-d | 9-b | 10-a |
| 11-b | 12-c | 13-d | 14-c | 15-b |
| 16-c | 17-b | 18-c | 19-d | 20-d |
| 21-b | 22-c | 23-d | 24-d | 25-d |
| 26-c | 27-b | 28-c | 29-b | 30-d |