1. The feature of Pentium 4 is
a) works based on NetBurst microarchitecture
b) clock speed ranges from 1.4GHz to 1.7GHz
c) has hyper-pipelined technology
d) all of the mentioned
1.7GHz. It has hyper-pipelined technology.
2. Which of the following is not a module of Pentium 4 architecture?
a) front end module
b) execution module
c) control module
d) none
3. The front module of Pentium 4 consists of
a) trace cache
b) microcode ROM
c) front end branch predictor
d) all of the mentioned
1. IA 32 Instruction decoder
2. Trace cache
3. Microcode ROM
4. Front end branch predictor
4. The unit that decodes the instructions concurrently and translate them into micro-operations is
a) trace cache
b) instruction decoder
c) execution module
d) front end branch predictor
5. In complex instructions, when the instruction needs to be translated into more than 4 micro-operations, then the decoder transfers the task to
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
6. The unit that does not store the instructions, but the decoded stream of instructions is
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
.
7. Trace cache can store the micro-ops upto a range of
a) 6 K decoded micro-ops
b) 8 K decoded micro-ops
c) 10 K decoded micro-ops
d) 12 K decoded micro-ops
8. The unit that predicts the locations from where the next instruction bytes are fetched is
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
9. If complex instructions like interrupt handling, string manipulation appear, then the control from trace cache transfers to
a) microcode ROM
b) front end branch predictor
c) execution module
d) instruction decoder
10. After the micro-ops are issued by the microcode ROM, the control goes to
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
11. The mechanism to provide protection, that is accomplished with the help of read/write privileges is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions
d) privileged operations
12. The Local descriptor table (LDT) and Global descriptor table (GDT) are present in
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
13. The mechanism that is accomplished using descriptor usages limitations, and rules of privilege check is
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
14. The mechanism that is executed at certain privilege levels, determined by CPL (Current Privilege Level) and I/O privilege level (IOPL) is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions or operations
d) none of the mentioned
15. If CPL is not of the required privilege level, then the instructions that get affected is
a) IRET
b) POPF
c) IRET and POPF
d) none of the mentioned
16. If CPL is greater than zero, then the instruction that remains unaffected is
a) IRET
b) POPF
c) IF
d) IRET and POPF
17. The condition, “CPL not equals to zero” satisfies, when executing the instruction
a) LIDT
b) LGDT
c) LTR
d) all of the mentioned
18. While executing the instruction IN/OUT, the condition of CPL is
a) CPL = 0
b) CPL < IOPL
c) CPL > IOPL
d) all of the mentioned
19. The instruction at which the exception is generated, but the processor extension registers containthe address of failing instruction is
a) LTR
b) INS
c) CTS
d) ESC
20. The exception that has no error code on stack is
a) double exception detected
b) processor extension segment overrun
c) invalid task state segment
d) stack segment overrun
21. By using privilege mechanism the protection from unauthorised accesses is done to
a) operating system
b) interrupt handlers
c) system softwares
d) all of the mentioned
22. The task privilege level at the instant of execution is called
a) Descriptor privilege level (DPL)
b) Current privilege level (CPL)
c) Effective privilege level (EPL)
d) none of the mentioned
23. Once the CPL is selected, it can be changed by
a) HOLD
b) transferring control using system descriptors
c) transferring control using gate descriptors
d) transferring control using interrupt descriptors
24. The data segments defined in GDT (global descriptor table) and the LDT (local descriptor table) can be accessed by a task with
a) privilege level 0
b) privilege level 1
c) privilege level 2
d) privilege level 3
25. A task with privilege level 0, doesnot refer to all the lower level privilege descriptors in
a) GDT (global descriptor table)
b) LDT (local descriptor table)
c) IDT (interrupt descriptor table)
d) none of the mentioned
26. The selector RPL that uses a less trusted privilege than the current privilege level for further use is known as
a) Least task privilege level
b) descriptor privilege level
c) effective privilege level
d) none of the mentioned
27. The effective privilege level is
a) maximum numeric of RPL and CPL
b) minimum privilege of RPL and CPL
c) numeric minimum and privilege maximum of RPL and CPL
d) none of the mentioned
28. The task requesting an access to a descriptor is allowed to access after checking the
a) type of descriptor
b) privilege level
c) type of descriptor and privilege level
d) corresponding segment
29. A CALL instruction can reference only a code segment descriptor with
a) DPL less privilege than CPL
b) DPL equal privilege to CPL
c) DPL greater privilege than CPL
d) all of the mentioned
30. The RPL of a selector that referred to the code descriptor must have
a) less privilege than CPL
b) greater privilege than CPL
c) equal privilege than CPL
d) any privilege regarding CPL
Answers
| 1-d | 2-c | 3-d | 4-b | 5-cc |
| 6-a | 7-d | 8-b | 9-a | 10-a |
| 11-a | 12-c | 13-b | 14-c | 15-c |
| 16-c | 17-d | 18-c | 19-d | 20-b |
| 21-d | 22-b | 23-c | 24-a | 25-b |
| 26-c | 27-c | 28-c | 29-b | 30-c |