Microprocessor Set 3 (30 mcqs)

1. The Stack follows the sequence
a) first-in-first-out
b) first-in-last-out
c) last-in-first-out
d) last-in-last-out

2. If the processor is executing a main program that calls a subroutine, then after executing the main program up to the CALL instruction, the control will be transferred to
a) address of main program
b) subroutine address
c) address of CALL instruction
d) none of the mentioned

3. The stack is useful for
a) storing the register status of the processor
b) temporary storage of data
c) storing contents of registers temporarily inside the CPU
d) all of the mentioned

4. The Stack is accessed using
a) SP register
b) SS register
c) SP and SS register
d) none

5. As the storing of data words onto the stack is increased, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2

6. While retrieving data from the stack, the stack pointer is
a) incremented by 1
b) incremented by 2
c) decremented by 1
d) decremented by 2

7. The process of storing the data in the stack is called ……… the stack.
a) pulling into
b) pulling out
c) pushing into
d) popping into

8. The reverse process of transferring the data back from the stack to the CPU register is known as
a) pulling out the stack
b) pushing out the stack
c) popping out the stack
d) popping off the stack

9. The books arranged one on the other on a table is an example of
a) queue
b) queue and first-in-first out
c) stack
d) stack and last-in-first-out

10. The PID temperature controller using 8086 has
a) data flow
b) data flow and uses queue
c) sequential flow
d) sequential flow and uses stack

11. The 32-bit control register, that is used to hold global machine status, independent of the executed task is
a) CR0
b) CR2
c) CR3
d) all of the mentioned

12. The descriptor table that the 80386 supports is
a) GDT (Global descriptor table)
b) IDT (Interrupt descriptor table)
c) LDT (Local descriptor table)
d) all of the mentioned

13. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR

14. Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) none of the mentioned

15. The test register(s) that is provided by 80386 for page cacheing is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers

16. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7

17. The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3

18. The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned

19. The flag bits that indicate the privilege level of current IO operations are
a) virtual mode flag bits
b) IOPL flag bits
c) resume flag bits
d) none of the mentioned

20. The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers

21. The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned

22. The size of the pages in paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none

23. To convert linear addresses into physical addresses, the mechanism that the paging unit uses is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism

24. The control register that stores the 32-bit linear address, at which the previous page fault is detected is
a) CR0
b) CR1
c) CR2
d) CR3

25. Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page

26. The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3

27. The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits

28. Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes

29. The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes

30. The dirty bit(D) is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned

Answers

 

1-c 2-b 3-d 4-c 5-d
6-b 7-c 8-d 9-d 10-d
11-d 12-d 13-a 14-b 15-c
16-b 17-d 18-a 19-b 20-c
21-d 22-b 23-d 24-c 25-b
26-d 27-d 28-b 29-c 30-a

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