1. Which of the following is a supporting chip of 80286?
a) interrupt controller
b) clock generator
c) bus controller
d) all of the mentioned
2. In minimum mode, the function of 80286 is
a) data transfers to/from memory or I/O
b) controls the data transfer of 80287
c) controls the instruction execution of 80287
d) all of the mentioned
3. The signal that is applied to the decoding logic, to differentiate between interrupt, code fetch and data bus cycles is
a) COD
b) INTA (active low)
c) M/IO (active low)
d) all of the mentioned
4. By adding which of the following, the minimum mode of 80286 gives the multibus interface of 80286?
a) bus controller
b) bus arbiter
c) interrupt controller
d) all of the mentioned
5. The number of bus controllers that are used for interfacing of memory and I/O devices is
a) 1
b) 2
c) 3
d) none of the mentioned
6. If the 80286 need to use system bus, then the signal that is to be active is
a) SRDY
b) SRDYEN
c) ARDYEN
d) ARDY
7. If MBYTES input is high, then the pin serves as
a) AEN
b) CEN
c) AEN and CEN
d) none of the mentioned
8. Latches are used in 80286 to
a) demultiplex the address and data lines
b) latch the address signals
c) decode the select signals
d) latch the address and decode the select signals
9. The I/O port addresses, that are not used, while designing practical systems around 80286 are
a) 0000H to 00FFH
b) 00FFH to FFFFH
c) 00F8H to 00FFH
d) 0000H to FFFFH
10. The instruction that multiplies the content of AL with a signed immediate operand is
a) MUL
b) SMUL
c) IMUL
d) none of the mentioned
11. The power control register is
a) used for power saving during idle state
b) used for eventual power off to 8051 chip
c) non-bit addressable register
d) all of the mentioned
12. The state of signals in idle mode is
a) ALE is high
b) PSEN is high
c) PSEN(active low) is high
d) ALE and PSEN(active low) are high
13. To come out of idle mode, the external interrupt that is enabled is
a) SI(serial)
b) INT0
c) INT1
d) all of the mentioned
14. The microcontroller enters into power down mode when
a) SMOD bit of PCON is set
b) GF1 bit of PCON is set
c) PD bit of PCON is set
d) GF2 bit of PCON is set
15. The clock signal is disabled to all parts of 8051 in
a) normal mode
b) idle mode
c) power down mode
d) addressing mode
16. During power down to save battery, the supply voltage can be reduced to a value of
a) 4 volts
b) 2 volts
c) 8 volts
d) 1 volt
17. The signal that only pulls the microcontroller(8051) out of the power down mode is
a) CLEAR
b) LEAVE
c) RESET
d) EXIT
18. The state of signals in power down mode is
a) ALE is high
b) PSEN is low
c) ALE and PSEN(active low) are high
d) ALE and PSEN(active low) are low
19. In power down mode,
a) port pins maintain their logic levels
b) SFRs maintain their logic levels
c) clock signal is disabled
d) all of the mentioned
.
20. The SMOD bit is used to
a) decrease the baud rate by 2
b) increase the baud rate by 4
c) increase the baud rate by 2
d) triple the baud rate
21. The instruction, MOV AX, 0005H belongs to the address mode
a) register
b) direct
c) immediate
d) register relative
22. The instruction, MOV AX, 1234H is an example of
a) register addressing mode
b) direct addressing mode
c) immediate addressing mode
d) based indexed addressing mode
.
23. The instruction, MOV AX, [2500H] is an example of
a) immediate addressing mode
b) direct addressing mode
c) indirect addressing mode
d) register addressing mode
.
24. If the data is present in a register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode
25. The instruction, MOV AX,[BX] is an example of
a) direct addressing mode
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode
26. If the offset of the operand is stored in one of the index registers, then it is
a) based indexed addressing mode
b) relative based indexed addressing mode
c) indexed addressing mode
d) none of the mentioned
27. The addressing mode that is used in unconditional branch instructions is
a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode
28. If the location to which the control is to be transferred lies in a different segment other than the current one, then the mode is called
a) intrasegment mode
b) intersegment direct mode
c) intersegment indirect mode
d) intersegment direct and indirect mode
29. The instruction, JMP 5000H:2000H;
is an example of
a) intrasegment direct mode
b) intrasegment indirect mode
c) intersegment direct mode
d) intersegment indirect mode
30. The contents of a base register are added to the contents of index register in
a) indexed addressing mode
b) based indexed addressing mode
c) relative based indexed addressing mode
d) based indexed and relative based indexed addressing mode
Answers
| 1-d | 2-d | 3-d | 4-b | 5-b |
| 6-c | 7-a | 8-d | 9-c | 10-c |
| 11-d | 12-d | 13-d | 14-c | 15-c |
| 16-b | 17-c | 18-d | 19-d | 20-c |
| 21-c | 22-c | 23-b | 24-b | 25-d |
| 26-c | 27-b | 28-d | 29-c | 30-d |